1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a fabrication method of a non-volatile memory.
2. Description of Related Art
In the various types of non-volatile memory, electrically erasable programmable read only memory (EEPROM) allows multiple data reading, writing and erasing operations. In addition, the stored data are retained even after power to the device is removed. With these advantages, electrically erasable programmable read only memories have been broadly applied in personal computers and electronic equipment.
The industry provides a type of non-volatile memory as shown in FIG. 1. This non-volatile memory is constituted with a plurality of memory cells 102 and a plurality of memory cells 116. The memory cells 102 and the memory cells 116 are isolated from each other with the spacers 110. Each memory cell 102 is formed, sequentially from the substrate 100, a bottom dielectric layer 104a, a charge-storage layer 104b and a top dielectric layer 104c (the bottom dielectric layer 104a, the charge-storage layer 104b and the top dielectric layer 104c constitute a composite dielectric layer 104), a gate 106 and a cap layer 108. Each memory cell 116 is disposed between two memory cells 102. Moreover, each memory cell 116 is formed, sequentially from the substrate 100, a bottom dielectric layer 112a, a charge-storage layer 112b and a top dielectric layer 112c (the bottom dielectric layer 112a, the charge—storage layer 112b and the top dielectric layer 112c constitute a composite dielectric layer 112) and a gate 114. No gap is present between each memory cell of this type of non-volatile memory. Accordingly, the level of integration can be increased.
However, during the fabrication process of the above non-volatile memory, the composite dielectric layer 104 of the memory cells 102 and the composite dielectric layer 112 of the memory cells 116 are formed in different process steps. As a result, the fabrication process is complicated. Moreover, since each memory cell 116 is formed between two memory cells 102, the composite dielectric layer 112 of the memory cells 116 is formed on a nonplanar surface. The thickness of the composite dielectric layer is not uniformed due to the corners formed between the memory cells 102 and the substrate 100. Consequently, the reliability of the memory cells is less desirable. Ultimately, the electrical characteristics between the memory cells 102 and the memory cells 116 are not consistent, greatly affecting the efficiency of the device.